1. Field of the Invention
The present invention relates to a method for manufacturing an ultra-large-scale integrated (ULSI) semiconductor memory device, and more particularly to a method for manufacturing a ULSI semiconductor memory device which can improve the performance of transistors of the peripheral circuit section.
2. Description of Related Art
As VLSI has become more integrated, 16 Mbit DRAMs have been mass-produced and new products related to 64 Mbit DRAMs have been presented. Such ULSI semiconductor memory devices require junctions which are as thin as possible and must take into consideration short-channel and hot-carrier effects, punch-through, the increase in breakdown voltage, etc., of a MOS transistor. If, on the other hand, the spacers formed on the side walls of the gate electrodes are wide, these thin junctions diffuse a short distance laterally, reducing the extent to which they are overlapped by the gate electrode, and therefore noticeably reducing the transistor's saturation drain current.
Accordingly, to control the width of a side wall spacer as desired, the thickness of a high temperature oxide (HTO) film which forms the side wall spacer should be controlled. However, since the HTO film is also used as a buffer layer for preventing silicon pitting during cell array capacitor formation, the thickness cannot be too thin.
That is, since the HTO film of the cell array is used to form side wall spacers for the transistors of the peripheral circuit section, the reduction of the width of the HTO-film side wall spacers is limited. This deteriorates the current driving capability of peripheral circuit transistors.
Referring to FIG. 1, in a NMOS transistor of lightly doped drain (LDD) structure, as length L1 of side wall spacer 1 increases, and in so doing, increasing length L2 of n.sup.- impurity-doped region 2, the resistance of region 2 increases. Accordingly, the drain saturation current is reduced. At the same time, increasing the dosage of the n.sup.- impurity to increase the drain saturation current does not sufficiently utilize the advantages of shallow junction xj1 since this would deteriorate punch-through tolerance.
Referring to FIG. 2, in a PMOS transistor of single drain structure, as length L1 of side wall spacer 3 increases, length L3 (with respect to p.sup.+ impurity-doped region 4 and gate electrode layer 5) increases. This also reduces drain saturation current. To increase the drain saturation current requires a complicated structure, such as an LDD structure, even in a PMOS transistor, the process becomes complex.